View AD8054_279822.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES Low Cost Single (AD8051), Dual (AD8052) and Quad (AD8054) Voltage Feedback Architecture Fully Specified at +3 V, +5 V and 5 V Supplies Single Supply Operation Output Swings to Within 25 mV of Either Rail Input Voltage Range: -0.2 V to +4 V; VS = +5 V High Speed and Fast Settling on +5 V: 110 MHz -3 dB Bandwidth (G = +1) (AD8051/AD8052) 150 MHz -3 dB Bandwidth (G = +1) (AD8054) 145 V/ s Slew Rate 50 ns Settling Time to 0.1% Small Packaging AD8051 Available in SOT-23-5 AD8052 Available in SOIC-8 AD8054 Available in TSSOP-14 Good Video Specifications (G = +2) Gain Flatness of 0.1 dB to 20 MHz; RL = 150 0.03% Differential Gain Error; RL = 1K 0.03 Differential Phase Error; R L = 1K Low Distortion -80 dBc Total Harmonic @ 1 MHz, RL = 100 Outstanding Load Drive Capability Drives 45 mA, 0.5 V from Supply Rails (AD8051/AD8052) Drives 50 pF Capacitive Load (G = +1) (AD8051/AD8052) Low Power of 2.75 mA/Amplifier (AD8054) Low Power of 4.4 mA/Amplifier (AD8051/AD8052) APPLICATIONS Coax Cable Driver Active Filters Video Switchers A/D Driver Professional Cameras CCD Imaging Systems CD/DVD ROM PRODUCT DESCRIPTION
NC 1 -IN 2 +IN 3 -VS 4
Low Cost, High Speed Rail-to-Rail Amplifiers AD8051/AD8052/AD8054
CONNECTION DIAGRAMS (Top Views) SO-8
AD8051
8 7 6 5
SOT-23-5 (RT)
NC +VS VOUT NC
VOUT 1 -VS 2 +IN 3
AD8051
5 +VS +- 4 -IN
NC = NO CONNECT
R-8, SOIC (RM)
OUT1 1 -IN1 2 +IN1 3 -VS 4
R-14, TSSOP-14 (RU-14)
OUT A IN A +IN A V+ +IN B IN B OUT B
1 2 3 4 5 6 7 14 13 12
AD8052
- + - +
8 7 6 5
+VS OUT -IN2 +IN2
OUT D IN D +IN D V +IN C IN C OUT C
AD8054
11 10 9 8
portable equipment. Low distortion and fast settling make them ideal for active filter applications. The AD8051/AD8052/AD8054 offer low power supply current and can operate on a single +3 V power supply. These features are ideally suited for portable and battery powered applications where size and power are critical. The wide bandwidth and fast slew rate on a single +5 V supply make these amplifiers useful in many general purpose, high speed applications where dual power supplies of up to 6 V and single supplies from +3 V to +12 V are needed. All of this low cost performance is offered in an 8-lead SOIC, along with a tiny SOT-23-5 package (AD8051), a SOIC package (AD8052) and a TSSOP-14 (AD8054).
5.0
0.5%) - Volts
The AD8051 (single), AD8052 (dual) and AD8054 (quad) are low cost, voltage feedback, high speed amplifiers designed to operate on +3 V, +5 V or 5 V supplies. They have true single supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. Despite their low cost, the AD8051/AD8052/AD8054 provide excellent overall performance and versatility. The output voltage swing extends to within 25 mV of each rail, providing the maximum output dynamic range with excellent overdrive recovery. This makes the AD8051/AD8052/AD8054 useful for video electronics such as cameras, video switchers or any high speed
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.1
VS = +5V G = -1 RF = 2k RL = 2k
(THD
1 FREQUENCY - MHz
10
50
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1. Low Distortion Rail-to-Rail Output Swing
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD8051/AD8052/AD8054-SPECIFICATIONS unless otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Conditions Min AD8051A/AD8052A Typ Max Min 70 G = +1, VO = 0.2 V p-p G = -1, +2, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p, RL = 150 to +2.5 V, RF = 806 for AD8051A/AD8052A RF = 200 for AD8054A 100 G = -1, VO = 2 V Step G = +1, VO = 2 V p-p G = -1, VO = 2 V Step 110 50 80
(@ TA = +25 C, VS = +5 V, RL = 2 k
AD8054A Typ
to +2.5 V,
Max
Units
150 60
MHz MHz
20 145 35 50 140 12 170 45 40
Slew Rate Full Power Response Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion1 Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) Crosstalk DC PERFORMANCE Input Offset Voltage
MHz MHz V/s MHz ns
fC = 5 MHz, VO = 2 V p-p, G = +2 f = 10 kHz f = 10 kHz G = +2, RL = 150 to +2.5 V RL = 1 k to +2.5 V G = +2, RL = 150 to +2.5 V RL = 1 k to +2.5 V f = 5 MHz, G = +2
-67 16 850 0.09 0.03 0.19 0.03 -60
-68 16 850 0.07 0.02 0.26 0.05 -60
dB nV/Hz fA/Hz % % Degrees Degrees dB
1.7 TMIN -T MAX 10 1.4 TMIN -T MAX 0.1 98 96 82 78
10 25 2.5 3.25 0.75 82 74
1.7 15 2 0.2 98 96 82 78
12 30 4.5 4.5 1.2
Offset Drift Input Bias Current Input Offset Current Open-Loop Gain
RL = 2 k to +2.5 V TMIN -T MAX RL = 150 to +2.5 V TMIN -T MAX
86 76
mV mV V/C A A A dB dB dB dB
INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing
VCM = 0 V to +3.5 V
72
290 1.4 -0.2 to 4 88
70
300 1.5 -0.2 to 4 86
k pF V dB
Output Current Short Circuit Current Capacitive Load Drive
RL = 10 k to +2.5 V RL = 2 k to +2.5 V RL = 150 to +2.5 V VOUT = 0.5 V to +4.5 V TMIN -T MAX Sourcing Sinking G = +1 (AD8051/AD8052) G = +2 (AD8054)
0.015 to 4.985 0.1 to 4.9 0.025 to 4.975 0.3 to 4.625 0.2 to 4.8 45 45 80 130 50
0.03 to 4.975 0.125 to 4.875 0.05 to 4.95 0.55 to 4.4 0.25 to 4.65 30 30 45 85 40
V V V mA mA mA mA pF pF
POWER SUPPLY Operating Range Quiescent Current/Amplifier Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
NOTES 1 Refer to Figure 15.
3 VS = 1 V 70 -40 4.4 80
12 5
3 68 2.75 80
12 V 3.275 mA dB +85 C
+85 -40
Specifications subject to change without notice.
-2-
REV. B
SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness
AD8051/AD8052/AD8054
(@ TA = +25 C, VS = +3 V, RL = 2 k
Conditions
to +1.5 V, unless otherwise noted)
Min AD8051A/AD8052A Typ 110 50 Max Min 80 AD8054A Typ 135 65 Max Units MHz MHz
Slew Rate Full Power Response Settling Time to 0.1%
70 G = +1, VO = 0.2 V p-p G = -1, +2, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p, RL = 150 to 2.5 V, RF = 402 for AD8051A/AD8052A RF = 200 for AD8054A G = -1, VO = 2 V Step 90 G = +1, VO = 1 V p-p G = -1, VO = 2 V Step
17 135 65 55 110 10 150 85 55
MHz MHz V/s MHz ns
NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion1 fC = 5 MHz, VO = 2 V p-p, G = -1, RL = 100 to +1.5 V Input Voltage Noise f = 10 kHz Input Current Noise f = 10 kHz Differential Gain Error (NTSC) G = +2, VCM = +1 V RL = 150 to +1.5 V, RL = 1 k to +1.5 V Differential Phase Error (NTSC) G = +2, VCM = +1 V RL = 150 to +1.5 V RL = 1 k to +1.5 V Crosstalk f = 5 MHz, G = +2 DC PERFORMANCE Input Offset Voltage TMIN -T MAX Offset Drift Input Bias Current TMIN -T MAX Input Offset Current Open-Loop Gain RL = 2 k TMIN -T MAX RL = 150 TMIN -T MAX 80 74
-47 16 600 0.11 0.09 0.24 0.10 -60
-48 16 600 0.13 0.09 0.3 0.1 -60
dB nV/Hz fA/Hz % % Degrees Degrees dB
1.6 10 1.3 0.15 96 94 82 76
10 25 2.6 3.25 0.8 80 72
1.6 15 2 0.2 96 94 80 76
12 30 4.5 4.5 1.2
mV mV V/C A A A dB dB dB dB
INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing
VCM = 0 V to 1.5 V
72
290 1.4 -0.2 to 2 88
70
300 1.5 -0.2 to 2 86
k pF V dB
Output Current Short Circuit Current Capacitive Load Drive
RL = 10 k to +1.5 V RL = 2 k to +1.5 V RL = 150 to +1.5 V VOUT = 0.5 V to +2.5 V TMIN -T MAX Sourcing Sinking G = +1 (AD8051/AD8052) G = +2 (AD8054)
0.01 to 2.99 0.075 to 2.9 0.02 to 2.98 0.2 to 2.75 0.125 to 2.875 45 45 60 90 45
0.1 to 2.9 0.35 to 2.55
0.025 to 2.98 0.35 to 2.965 0.15 to 2.75 25 25 30 50 35
V V V mA mA mA mA pF pF
POWER SUPPLY Operating Range Quiescent Current/Amplifier Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
NOTES 1 Refer to Figure 15.
3 VS = +0.5 V 68 -40 4.2 80
12 4.8
3 68 2.625 80
12 V 3.125 mA dB +85 C
+85 -40
Specifications subject to change without notice.
REV. B
-3-
AD8051/AD8052/AD8054-SPECIFICATIONS unless otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Conditions Min AD8051A/AD8052A Typ Max Min G = +1, VO = 0.2 V p-p 70 G = -1, +2, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p, RL = 150 , RF = 1.1 k for AD8051A/AD8052A RF = 200 for AD8054A G = -1, V O = 2 V Step 105 G = +1, VO = 2 V p-p G = -1, V O = 2 V Step 110 50 85
(@ TA = +25 C, VS =
5 V, RL = 2 k
to Ground,
AD8054A Typ
Max Units
160 65
MHz MHz
20 170 40 50 150 15 190 50 40
Slew Rate Full Power Response Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) Crosstalk DC PERFORMANCE Input Offset Voltage
MHz MHz V/s MHz ns
fC = 5 MHz, VO = 2 V p-p, G = +2 f = 10 kHz f = 10 kHz G = +2, RL = 150 RL = 1 k G = +2, RL = 150 RL = 1 k f = 5 MHz, G = +2
-71 16 900 0.02 0.02 0.11 0.02 -60
-72 16 900 0.06 0.02 0.15 0.03 -60
dB nV/Hz fA/Hz % % Degrees Degrees dB
1.8 TMIN -TMAX 10 1.4 TMIN -TMAX 0.1 96 96 82 80
11 27 2.6 3.5 0.75 84 76
1.8 15 2 0.2 96 96 82 80
13 32 4.5 4.5 1.2
Offset Drift Input Bias Current Input Offset Current Open-Loop Gain
RL = 2 k TMIN -TMAX RL = 150 TMIN -TMAX
88 78
mV mV V/C A A A dB dB dB dB
INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing
VCM = -5 V to +3.5 V
72
290 1.4 -5.2 to 4 88
70
300 1.5 -5.2 to 4 86
k pF V dB
Output Current Short Circuit Current Capacitive Load Drive
RL = 10 k RL = 2 k RL = 150 VOUT = -4.5 V to +4.5 V TMIN -TMAX Sourcing Sinking G = +1 (AD8051/AD8052) G = +2 (AD8054)
-4.98 to +4.98 -4.85 to +4.85 -4.97 to +4.97 -4.45 to +4.3 -4.6 to +4.6 45 45 100 160 50
-4.97 to +4.97 -4.8 to +4.8 -4.9 to +4.9 -4.0 to +3.8 -4.5 to +4.5 30 30 60 100 40
V V V mA mA mA mA pF pF
POWER SUPPLY Operating Range Quiescent Current/Amplifier Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
3 VS = 1 V 68 -40 4.8 80
12 5.5
3 68 2.875 80
12 3.4
V mA dB C
+85
-40
+85
Specifications subject to change without notice.
-4-
REV. B
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION - Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Small Outline Package (R) . . . Observe Power Derating Curves SOT-23-5 Package . . . . . . . . Observe Power Derating Curves SOIC Package . . . . . . . . . . Observe Power Derating Curves TSSOP-14 Package . . . . . . . Observe Power Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (R) . . . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead SOIC: JA = 155C/W 5-Lead SOT-23-5: JA = 240C/W 8-Lead SOIC: JA = 200C/W 14-Lead SOIC: JA = 120C/W 14-Lead TSSOP: JA = 180C/W
plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8051/AD8052/AD8054 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
14-LEAD SOIC
1.5 8-LEAD SOIC PACKAGE
TJ = +150 C
1.0
14-LEAD TSSOP-14
0.5
SOIC SOT-23-5
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8051/ AD8052/AD8054 is limited by the associated rise in junction temperature. The maximum safe junction temperature for
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE - C
Figure 2. Plot of Maximum Power Dissipation vs. Temperature for AD8051/AD8052/AD8054
ORDERING GUIDE
Model AD8051AR AD8051AR-REEL AD8051AR-REEL7 AD8051ART-REEL AD8051ART-REEL7 AD8052AR AD8052AR-REEL AD8052AR-REEL7 AD8052ARM AD8052ARM-REEL AD8052ARM-REEL7 AD8054AR AD8054AR-REEL AD8054AR-REEL7 AD8054ARU AD8054ARU-REEL AD8054ARU-REEL7
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Descriptions 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 13" Tape and Reel 7" Tape and Reel 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 14-Lead SOIC 13" Tape and Reel 7" Tape and Reel 14-Lead SOIC 13" Tape and Reel 7" Tape and Reel
Package Options* SO-8 SO-8 SO-8 RT-5 RT-5 SO-8 SO-8 SO-8 RM-8 RM-8 RM-8 R-14 R-14 R-14 RU-14 RU-14 RU-14
Brand Code
H2A H2A
H4A H4A H4A
*R = Small Outline; RM = Micro Small Outline; RT = Surface Mount; RU = TSSOP .
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8051/AD8052/AD8054 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-5-
AD8051/AD8052/AD8054
3 2 1 NORMALIZED GAIN - dB 0 -1 -2 -3 -4 -5 -6 -7 0.1 VS = +5V GAIN AS SHOWN RF AS SHOWN RL = 2k VO = 0.2V p-p 1 10 FREQUENCY - MHz 100 500 G = +10 RF = 2k G = +2 RF = 2k
NORMALIZED GAIN - dB 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 100k 1M G = +5 RF = 2k 10M FREQUENCY - Hz 100M 500M G = +10 RF = 2k VS = +5V GAIN AS SHOWN RF AS SHOWN RL = 5k VO = 0.2V p-p G = +2 RF = 2k G = +1 RF = 0
G = +5 RF = 2k
G = +1 RF = 0
Figure 3. AD8051/AD8052 Normalized Gain vs. Frequency; VS = +5 V
Figure 6. AD8054 Normalized Gain vs. Frequency; VS = +5 V
3 2 VS = +3V 1 0 GAIN - dB VS = +5V
6 5 4 3 G = +1 RL = 2k CL = 5pF VO = 0.2V p-p +3V +5V 5V
-2 -3 -4 -5 -6 -7 0.1
GAIN - dB
-1 VS AS SHOWN G = +1 RL = 2k VO = 0.2V p-p
VS =
5V
2 1 0 -1 -2 +3V -3 +5V 1M 10M FREQUENCY - Hz 100M 500M 5V
1
10 FREQUENCY - MHz
100
500
-4 100k
Figure 4. AD8051/AD8052 Gain vs. Frequency vs. Supply
Figure 7. AD8054 Gain vs. Frequency vs. Supply
3 2 1 0
GAIN - dB
GAIN - dB
4 3 +85 C +25 C -40 C
-40 C
2
-1 -2 -3 VS = +5V G = +1 -5 RL = 2k VO = 0.2V p-p -6 TEMPERATURE AS SHOWN -4 -7 0.1 1
+85 C +25 C
1 0 -1 -2 -3 -4 -5 VS = +5V RL = 2k TO 2.5V CL = 5pF G = +1 VO = 0.2V p-p
10 FREQUENCY - MHz
100
500
1
10 FREQUENCY - MHz
100
500
Figure 5. AD8051/AD8052 Gain vs. Frequency vs. Temperature
Figure 8. AD8054 Gain vs. Frequency vs. Temperature
-6-
REV. B
AD8051/AD8052/AD8054
6.3 6.2 6.1
GAIN FLATNESS - dB GAIN FLATNESS - dB 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 5.4 5.3 1 10 FREQUENCY - MHz 100 VS = +5V RF = 200 RL = 150 G = +2 VO = 0.2V p-p
6.0 5.9 5.8 5.7 5.6 5.5 5.4 5.3 0.1 1 10 FREQUENCY - MHz 100 VS = +5V G = +2 RL = 150 RF = 806 VO = 0.2V p-p
Figure 9. AD8051/AD8052 0.1 dB Gain Flatness vs. Frequency; G = +2
Figure 12. AD8054 0.1 dB Gain Flatness vs. Frequency; G = +2
9 8 7 6
GAIN - dB
9
VS = +5V VO = 2V p-p
8 7 6 GAIN - dB 5 4 3 2 1 0 VS AS SHOWN G = +2 RL = 2k RF = 2k VO AS SHOWN 1 VS = 5V VO = 4V p-p
VS = +5V VO = 2V p-p
5 4 3 2 1 0 -1 0.1 VS AS SHOWN G = +2 RL = 2k RF = 2k VO AS SHOWN 1 VS = 5V VO = 4V p-p
10 FREQUENCY - MHz
100
500
-1 0.1
10 FREQUENCY - MHz
100
500
Figure 10. AD8051/AD8052 Large Signal Frequency Response; G = +2
Figure 13. AD8054 Large Signal Frequency Response; G = +2
80 70 60 VS = +5V RL = 2k
80 70 60 OPEN-LOOP GAIN - dB 50 40 30 20 PHASE 10 0 -10 -20 30k 100k 1M 10M FREQUENCY - Hz 100M 45 PHASE MARGIN GAIN 180 135 90 45 0 500M PHASE MARGIN - Degrees VS = +5V RL = 2k CL = 5pF
OPEN-LOOP GAIN - dB
50 40 30 20 PHASE 10 0 -10 -20 0.01 0.1 1 10 FREQUENCY - MHz 100 50 PHASE MARGIN GAIN
-45 -90 -135 -180 500
Figure 11. AD8051/AD8052 Open-Loop Gain and Phase vs. Frequency
PHASE - Degrees
0
Figure 14. AD8054 Open-Loop Gain and Phase Margin vs. Frequency
REV. B
-7-
AD8051/AD8052/AD8054
20 VO = 2V p-p
TOTAL HARMONIC DISTORTION - dBc
1000
30 40 50 60 70 80 90 100 110 1 VS = +5V, G = +2 RF = 2k , RL = 2k
VS = +3V, G = 1 RF = 2k , RL = 100
VOLTAGE NOISE - nA Hz
VS = +5V
VS = +5V, G = +2 RF = 2k , RL = 100 VS = +5V, G = +1 RL = 100
100
VS = +5V, G = +1 RL = 2k
10
2 3 4 5 67 FUNDAMENTAL FREQUENCY - MHz
8 9 10
1 10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
Figure 15. Total Harmonic Distortion
Figure 18. Input Voltage Noise vs. Frequency
30 40 50
WORST HARMONIC - dBc
100 VS = +5V
10MHz
CURRENT NOISE - pA Hz
60 70 80 90 100 110 120 130 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE - V p-p 4.0 4.5 5.0 1MHz VS = +5V RL = 2k G = +2 5MHz
10
1
0.1 10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
Figure 16. Worst Harmonic vs. Output Voltage
Figure 19. Input Current Noise vs. Frequency
0.10 0.08 0.06 0.04 0.02 0.00 0.02 0.04 0.06 0.10 0.05 0.00 0.05 0.10 0.15 0.20 0.25
0.10
DIFFERENTIAL GAIN ERROR - %
DIFFERENTIAL GAIN - %
NTSC SUBSCRIBER (3.58MHz)
RL = 150
NTSC SUBSCRIBER (3.58MHz) 0.05 0.00 -0.05 VS = +5, G = +2 RF = 2k , RL AS SHOWN -0.10 1st 2nd 3rd 4th 5th 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 VS = +5, G = +2 RF = 2k , RL AS SHOWN 1st 2nd RL = 1k RL = 1k
VS = +5, G = +2 RF = 2k , RL AS SHOWN 0 10 20 30 40 50 60
RL = 1k
RL = 150 6th 7th 8th 9th 10th 11th
70
80
90
100
DIFFERENTIAL PHASE - Degrees
DIFFERENTIAL PHASE ERROR - Degrees
RL = 1k
RL = 150 VS = +5, G = +2 RF = 2k , RL AS SHOWN 0 10 20 30 40 50 60 70 80 MODULATING RAMP LEVEL - IRE 90 100
RL = 150
3rd 4th 5th 6th 7th 8th 9th 10th 11th MODULATING RAMP LEVEL - IRE
Figure 17. AD8051/AD8052 Differential Gain and Phase Errors
Figure 20. AD8054 Differential Gain and Phase Errors
-8-
REV. B
AD8051/AD8052/AD8054
-10 -20 -30 VS = +5V RF = 2k RL = 2k VO = 2V p-p
-10 -20 -30
CROSSTALK - dB
CROSSTALK - dB
-40 -50 -60 -70 -80
-40 -50 -60 -70 -80 -90 RL = 1k VS = 5V RF = 1k RL = AS SHOWN VO = 2V p-p RL = 100
-90 -100 0.1
-100
1 10 FREQUENCY - MHz 100 500
-110 0.1
1
10 FREQUENCY - MHz
100
500
Figure 21. AD8052 Crosstalk (Output-to-Output) vs. Frequency
Figure 24. AD8054 Crosstalk (Output-to-Output) vs. Frequency
0 -10 -20 -30
CMRR - dB
PSRR - dB
20 VS = +5V 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0.01 +PSRR -PSRR VS = +5V
-40 -50 -60 -70 -80 -90
-100 0.03
0.1
1 10 FREQUENCY - MHz
100
500
0.1
1 10 FREQUENCY - MHz
100
500
Figure 22. CMRR vs. Frequency
Figure 25. PSRR vs. Frequency
100 31 10 3.1 1 0.31 0.1 VS = 5V G= 1
70 60
ns
AD8051/AD8052
OUTPUT RESISTANCE -
SETTING TIME TO 0.1%
50 AD8054 40 30 20 10 0 0.5 VS = 5V G= 1 RL = 2k 1 1.5 INPUT STEPS - Volts p-p 2
0.031 0.01 0.1
1
10 FREQUENCY - MHz
100
500
Figure 23. Closed Loop Output Resistance vs. Frequency
Figure 26. Settling Time vs. Input Step
REV. B
-9-
AD8051/AD8052/AD8054
1.00
1.00 OUTPUT SATURATION VOLTAGE - Volts
OUTPUT SATURATION VOLTAGE - Volts
0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 0
VOH = +85 C VOH = +25 C VOH = -40 C
VS = +5V
VS = +5V 0.875 0.750 +5V -VOH (+25 C) 0.625 0.500 0.375 0.250 VOL (+125 C) 0.125 VOL (-55 C) 0.00 0 3 6 9 VOL (+25 C) 24 27 30 +5V -VOH (-55 C) +5V -VOH (+125 C)
VOL = +85 C
VOL = +25 C VOL = -40 C
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 LOAD CURRENT - mA
12 15 18 21 LOAD CURRENT - mA
Figure 27. AD8051/AD8052 Output Saturation Voltage vs. Load Current
Figure 29. AD8054 Output Saturation Voltage vs. Load Current
100 RL = 2k
OPEN-LOOP GAIN - dB
90
RL = 150 80
70 VS = +5V
60 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE - Volts 4 4.5 5
Figure 28. Open-Loop Gain vs. Output Voltage
-10-
REV. B
AD8051/AD8052/AD8054
5
VOLTS
VOLTS
1.50V
2.5
Figure 30. 100 mV Step Response, G = +1
Figure 33. Output Swing; G = -1, RL = +2 k
2.60
2.55
2.50
2.50
2.40
2.45
20ns
Figure 31. AD8051/AD8052 200 mV Step Response; VS = +5 V, G = +1
Figure 34. AD8054 100 mV Step Response; VS = +5 V, G = +1
4 3
3.5
VOLTS
2 1
2.5
1
1.5
2 3 4
Figure 32. Large Signal Step Response; VS = +5 V, G = +2
Figure 35. Large Signal Step Response; VS = 5 V, G = +1
REV. B
-11-
AD8051/AD8052/AD8054
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 36, the AD8051/AD8052/ AD8054 recovers within 60 ns from negative overdrive and within 45 ns from positive overdrive.
2.60 2.55 2.50 2.45 2.40
Figure 38. AD8051/AD8052 200 mV Step Response: CL = 50 pF
10000 VS = +5V 30% OVERSHOOT
PF
Figure 36. Overdrive Recovery
Driving Capacitive Loads
RS = 3
1000 RS = 0
Consider the AD8051/AD8052 in a closed-loop gain of +1 with +VS = 5 V and a load of 2 k in parallel with 50 pF. Figures 37 and 38 show its frequency and time domain responses, respectively, to a small-signal excitation. The capacitive load drive of the AD8051/AD8052/AD8054 can be increased by adding a low valued resistor in series with the load. Figures 39 and 40 show the effect of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less peaking. Adding a series resistor with lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and the load capacitance.
8 6 4 2 0 2 4 6 8 10 0.1 VS = +5V G = +1 RL = 2k CL = 50pF VO = 200mV p-p 500
CAPACITIVE LOAD
100 RG 10 VIN 100mV STEP 50 RF RS VOUT CL
1
1
2
3
4 A C L - V/V
5
6
Figure 39. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain
1000 VS = +5V 30% OVERSHOOT
CAPACITIVE LOAD - pF
RS = 10
GAIN - dB
RS = 0 100
RG VIN 100mV STEP 50
RF RS VOUT CL
1
10 FREQUENCY - MHz
100
10 1 2 3 4 A C L - V/V 5 6
Figure 37. AD8051/AD8052 Closed-Loop Frequency Response: CL = 50 pF
Figure 40. AD8054 Capacitive Load Drive vs. Closed-Loop Gain
Circuit Description
The AD8051/AD8052/AD8054 is fabricated on Analog Devices' proprietary eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz-4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up -12- REV. B
AD8051/AD8052/AD8054
problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 1). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of -80 dBc @ 1 MHz into 100 with VOUT = 2 V p-p (Gain = +1) on a single 5 V supply is achieved. The inputs of the device can handle voltages from -0.2 V below the negative rail to within 1 V of the positive rail. Exceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 V. During this overdrive condition, the output stays at the rail. The rail-to-rail output range of the AD8051/AD8052/AD8054 is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8051/AD8052 to drive 45 mA of output current and the AD8054 to drive 30 mA of output current with the outputs within 0.5 V of the supply rails.
VCC R26 Q4 R15 R2 VINP VINN SIP Q2 SIN Q11 Q24 R3 I7 Q47 I11 I8 VCC
GAIN - dB
to a minimum. Parasitic capacitance of less than 1 pF at the inverting input can significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 25 mm). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end.
Active Filters
Active filters at higher frequencies require wider bandwidth op amps to work effectively. Excessive phase shift produced by lower frequency op amps can significantly impact active filter performance. Figure 42 shows an example of a 2 MHz biquad bandwidth filter that uses three op amps of an AD8054. Such circuits are sometimes used in medical ultrasound systems to lower the noise bandwidth of the analog signal before A/D conversion. Please note that the unused amplifiers' inputs should be tied to ground.
R6 1k C1 50pF R2 2k VIN R1 3k 2 1 3 R3 2k 13 C2 50pF 7 5 R5 2k 9 8 10 VOUT 14 12
R4 2k 6
I10
R39 Q5
Q25 I2 I3 Q51
Q50 Q39 Q23
I9 Q36 I5 VEE C3 VOUT C9
AD8054 AD8054
AD8054
Q40 VEE Q22 Q7 Q21 Q27 R23 R27 Q31
Figure 42. 2 MHz Biquad Bandpass Filter Using AD8054
The frequency response of the circuit is shown in Figure 43.
Q13
Q1
0
Q8
Q3 R5 R21
10
C7 VEE
Figure 41. AD8051/AD8052 Simplified Schematic
APPLICATIONS Layout Considerations
20
30
The specified high speed performance of the AD8051/AD8052/ AD8054 requires careful attention to board layout and component selection. Proper RF design techniques and low-parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the parasitic capacitance. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within 3 mm of each power pin. An additional large (4.7 F to 10 F) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the parasitic capacitance at this node REV. B
40 10k 100k 1M FREQUENCY - Hz 10M 100M
Figure 43. Frequency Response of 2 MHz Bandpass Biquad Filter
A/D and D/A Applications
Figure 44 is a schematic showing the AD8051 used as a driver for an AD9201, a 10-bit 20 MSPS dual A/D converter. This converter is designed to convert I and Q signals in communication systems. In this application, only the I channel is being driven. The I channel is enabled by applying a logic HIGH to SELECT, Pin 27. The AD8051 is running from a dual supply and is configured for a gain of +2. The input signal is terminated in 50 and -13-
AD8051/AD8052/AD8054
0.33 F +5V 10 F 0.01 F 22 50 1k 0.1 F 22 10pF 22 INB-I 10pF REFT-I 0.1 F 10 F 0.1 F 1k 0.1 F 5V 1k 0.1 F 10 F 0.1 F 22 10pF 22 INA-Q 10pF THREE-STATE INB-Q 0.1 F 10 F 5V 10 F 10 F 0.1 F 0.1 F 0.1 F REFB-I AVSS REFSENSE VREF AVDD REFB-Q REFT-Q SLEEP INA-I CLK SELECT VDD
AD9201
DATA OUT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD DVSS 0.1 F 10 F 5V
AD8051
Figure 44. AD8051 Driving an AD9201, a 10-Bit 20 MSPS A/D Converter
applied to the noninverting input of the AD8051. The amplifier output is 2 V p-p, which is the maximum input range of the AD9201. The 22 series resistor limits the maximum current that flows and helps to lower the distortion of the A/D. The AD9201 has differential inputs for each channel. These are designated the A and B inputs. The B inputs of each channel are connected to VREF (Pin 8) which supplies a positive reference of 2.5 V. Each of the B inputs has a small low pass filter that also helps to reduce distortion. The output of the op amp is ac coupled into INA-I (Pin 2) via two parallel capacitors to provide good high frequency and low frequency coupling. The 1 k resistor references the signal to VREF that is applied to INB-I. Thus, INA-I will swing both
positive and negative with respect to the bias voltage applied to INB-I. With the sampling clock running at 20 MSPS, the A/D output was analyzed with a digital analyzer. Two input frequencies were used, 1 MHz and 9.5 MHz, which is just short of the Nyquist frequency. These signals were well filtered to minimize any harmonics. Figure 45 shows the FFT response of the A/D for the case of 1 MHz analog input. The SFDR is 71.66 dB and the A/D is producing 8.8 ENOB (effective number of bits). When the analog frequency was raised to 9.5 MHz, the SFDR was reduced to 60.18 dB and the A/D operated with 8.46 ENOBs as shown in Figure 46. The inclusion of the AD8051 in the circuit had no worsening of the distortion performance of the AD9201.
10.0 5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 105.0 110.0 115.0 120.0 0.0E 0 1.0E 6
2ND 3RD
10.0 5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 105.0 110.0 115.0 120.0 0.0E 0
PART#
FUND
0 20.0E 6 998.5E 3 0.51dB 68.13 54.97 54.76 8.80 71.66 74.53 76.06 76.35 79.05 80.36 75.08 88.12 77.87
PART#
FUND
0 20.0E 6 9.5E 6 0.44dB 57.08 54.65 52.69 8.46 60.18 60.18 60.23 82.01 78.83 81.28 77.28 84.54 92.78
FFTSIZE 8192
FFTSIZE 8192
FCLK FUND VIN THD SNR SINAD ENOB SFDR 2ND 3RD 4TH 5TH
2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH
FCLK FUND VIN THD SNR SINAD ENOB SFDR 2ND 3RD 4TH 5TH
7TH 4TH 6TH 8TH
6TH 7TH 8TH 9TH
6TH 7TH 8TH 9TH
2.0E 6 1.0E 6 3.0E 6
4.0E 6 5.0E 6
6.0E 6 7.0E 6
8.0E 6
10.0E 6 9.0E 6
2.0E 6 3.0E 6
4.0E 6 5.0E 6
6.0E 6 7.0E 6
8.0E 6
10.0E 6 9.0E 6
Figure 45. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
Figure 46. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
-14-
REV. B
AD8051/AD8052/AD8054
Sync Stripper
Synchronizing pulses are sometimes carried on video signals so as not to require a separate channel to carry the synchronizing information. However, for some functions, like A/D conversion, it is not desirable to have the sync pulses on the video signal. These pulses will reduce the dynamic range of the video signal and do not provide any useful information for such a function. A sync stripper will remove the synchronizing pulses from a video signal while passing all the useful video information. Figure 47 shows a practical single supply circuit that uses only a single AD8051. It is capable of directly driving a reverse terminated video line.
VIDEO WITH SYNC VIDEO WITHOUT SYNC
goes high with a duty cycle that is a small fraction of a percent. The opposite condition defines the other extreme. The worst case of composite video is not quite this demanding. One bounding condition is a signal that is mostly black for an entire frame, but has a white (full amplitude) minimum width spike at least once in a frame. The other extreme is for a full white video signal. The blanking intervals and sync tips of such a signal will have negative-going excursions is compliance with the composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at the highest (white) level for a maximum of about 75% of the time. As a result of the duty cycles between the two extremes presented above, a 1 V p-p composite video signal that is multiplied by a gain of two requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary varying duty cycle without distortion. Some circuits use a sync tip clamp to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. However, these circuits can have artifacts like sync tip compression unless they are driven by a source with a very low output impedance. The AD8051/AD8052/AD8054 have adequate signal swing when running on a single +5 V supply to handle an ac coupled composite video signal. The input to the circuit in Figure 48 is a standard composite (1 V p-p) video signal that has the blanking level at ground. The input network level shifts the video signal by means of ac coupling. The noninverting input of the op amp is biased to half of the supply voltage. The feedback circuit provides unity gain for the dc biasing of the input, and provides a gain of two for any signals that are in the video bandwidth. The output is ac coupled and terminated to drive the line. The capacitor values were selected for providing minimum "tilt" or field time distortion of the video signal. These values would be required for video that is considered to be studio or broadcast quality. However, if a lower consumer grade of video, sometimes referred to as "consumer video" is all that is desired, the values and the cost of the capacitors can be reduced by as much as a factor of five with minimum visible degradation in the picture.
+5V 4.99k 4.99k COMPOSITE 47 F VIDEO + IN RT 10 F 75 + 10 F 0.1 F +
VBLANK GROUND
+0.4V
GROUND
+3V OR +5V 0.1 F VIN + 10 F TO A/D 100 R2 1k R1 1k +0.8V (OR 2 VBLANK)
AD8051
Figure 47. Sync Stripper
The video signal plus sync is applied to the noninverting input with the proper termination. The amplifier gain is set equal to two via the two 1 k resistors in the feedback circuit. A bias voltage must be applied to R1 in order that the input signal has the sync pulses stripped at the proper level. The blanking level of the input video pulse is the desired place to remove the sync information. This level is multiplied by two by the amplifier. This level must be at ground at the output in order for the sync stripping action to take place. Since the gain of the amplifier from the input of R1 to the output is -1, a voltage equal to 2 x VBLANK must be applied to make the blanking level come out at ground.
Single Supply Composite Video Line Driver
Many composite video signals have their blanking level at ground and have video information that is both positive and negative. Such signals require dual supply amplifiers to pass them. However, by ac level shifting a single supply amplifier can be used to pass these signals. The following complications may arise from such techniques. Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capacity than their (bounded) peak to peak amplitude after they are ac coupled. As a worst case, the dynamic signal swing will approach twice the peakto-peak value. The two conditions that define the maximum dynamic wing requirements are a signal that is mostly low, but
10 F RBT 75 RL 75
AD8051
RF 1k
1000 F +
VOUT
0.1 F
RG 1k 220 F
Figure 48. Single Supply Composite Video Line Driver
REV. B
-15-
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
8-Lead SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90)
8
5
14
8
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
0.177 (4.50) 0.169 (4.30)
1
0.256 (6.50) 0.246 (6.25)
7
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.028 (0.71) 0.016 (0.41) 0.120 (3.05) 0.112 (2.84)
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
5-Lead Plastic Surface Mount (RT-5)
0.1220 (3.100) 0.1063 (2.700)
0.0709 (1.800) 0.0590 (1.500) PIN 1
5
4
1
2
3
0.1181 (3.000) 0.0984 (2.500)
0.0374 (0.950) REF 0.0748 (1.900) REF 0.0512 (1.300) 0.0354 (0.900) 0.0590 (0.150) 0.0000 (0.000) 0.0571 (1.450) 0.0354 (0.900) 0.0197 (0.500) 0.0118 (0.300) SEATING PLANE 10 0
0.0079 (0.200) 0.0035 (0.090)
0.0236 (0.600) 0.0039 (0.100)
-16-
REV. B
PRINTED IN U.S.A.
C3139b-0-9/99

▲Up To Search▲

Price & Availability of AD8054

	To Download AD8054 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .